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2–2
Chapter 2: Getting Started
Design Flow
Figure 2–1 shows the system-level design flow using DSP Builder.
Figure 2–1. System-Level Design Flow
The design flow involves the following steps:
1. Use the MathWorks software to create a model with a combination of Simulink
and DSP Builder blocks.
1
Separate The DSP Builder blocks in your design from the Simulink blocks
by Input and Output blocks from the DSP Builder IO and Bus library.
2. Include a Clock block from the DSP Builder AltLab library to specify the base clock
for your design, which must have a period greater than 1ps but less than 2.1 ms.
1
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
If no base clock exists in your design, DSP Builder creates a default clock
with a 20ns real-world period and a Simulink sample time of 1. You can
derive additional clocks from the base clock by adding Clock_Derived
blocks.
November 2013 Altera Corporation
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